1. Field of Invention
This invention relates generally to analog to digital converters and more specifically to calibration of analog to digital converters.
2. Discussion of Related Art
Analog to digital converters are used in many modern electronic systems. Many electrical signals are analog—meaning that the signal can take on any value in a range of values. However, many components in electronic systems operate on digital signals—meaning that the value of the signal is represented at any time by “bits” of data, with each bit taking on only one of two possible states. Accordingly, there is a need for analog to digital converters to allow analog signals to be processed in digital form.
FIG. 1 shows in simplified block diagram form a prior art analog to digital converter. Analog to digital converter (ADC) 100 receives an analog input Sin and produces a digital output 120.
Analog input Sin is applied to a buffer amplifier 112. The output of buffer amplifier 112 is applied to a chain of separate stages 114A, 114B . . . 114N. Usually, these stages are pipelined.
Each of the stages 114A, 114B . . . 114N receives an analog input and produces a digital output. The digital outputs of the stages are applied to digital logic 116. Each stage also produces an analog output that is passed on to the next stage. The analog output of the stage is a residue, representing the difference between the analog input of the stage and the value corresponding to the digital output of that stage. Because each stage represents its input with a finite number of digital bits, the digital representation produced at each of the stages is not an exact representation of the value of the analog input. However, at each stage the residue becomes smaller, meaning that the collective outputs of all of the stages becomes a more accurate representation of the analog input Sin as outputs of more stages are produced.
Digital logic 116 combines the outputs of all of the stages 114A, 114B . . . 114N into a binary output 118. In general, it is not necessary that there be a one-to-one correspondence between the output bits of the stages and the bits of the digital word 118. For example, stage 114A might produce digital outputs that could take on one of six possible states. Stage 114B might have digital output bits that represent one of three possible states. The combination of the output bits from the first two stages form the four most significant bits of the digital word 118. The output of stage 114B would also influence the output of the fifth most significant bit. Digital logic 116 is constructed to make the appropriate combination of bits from all of the stages 114A . . . 114N to produce a digital word 118. In this way, the digital output 120 of ADC 100 represents the analog input Sin.
Even though each stage has a limited number of bits and cannot exactly represent the input, it is desirable for each stage to output a digital value that is as close as possible to the value of the analog input to that stage. However, variations in manufacturing processes and other real-world phenomena often preclude the construction of stages that always respond as desired. In practice, calibration circuitry is included in an ADC. Measurements are made on an ADC to detect differences between the actual and expected performance. The calibration circuitry is set to counteract differences between actual and desired performance of the ADC.
ADC 100 is shown to include calibration circuitry in the form of calibration memories 130A, 130B, 130C . . . 130N. These calibration memories hold values that map the output values produced by each of the stages as nearly as possible to the desired values.
As part of the manufacture of ADC 100, a calibration process is used to determine calibration values for memories 130A . . . 130N. A series of test inputs is applied to ADC 100 and the output of the converter observed. Differences between the actual digital output of the analog to digital converter and the expected output based on the value of the analog input can be measured. The measurement of the difference can be used to compute calibration values. These calibration values are stored in memories 130A . . . 130N.
However, it is difficult to determine what calibration values to store in the memories. Because there is not a one-to-one relationship between the output digital bits and the output of the individual stages, it is difficult to identify the values of outputs of stages 114A . . . 114N from the digital word observable at the output 120 of ADC 100. For this reason, prior art ADC's have been limited in the number of stages having calibration memories. Generally, only the first stage or two included such a memory.
FIG. 2A shows a transfer function of an idealized ADC. Line 210 shows that as the analog input increases, the digital output increases. Line 210 depicts a series of steps. These steps result from the fact that the ADC can represent only a finite number of values. The idealized ADC produces an output that matches the input value to the closest one of these finite values. As the analog input increases and comes closer to the next higher value that can be represented, the digital output steps up. These steps are evenly centered around line 200, showing the linear relationship between the input and the output.
FIG. 2B shows the same type of plot for a realistic, or non-idealized, ADC. As in FIG. 2A, the output values increase in steps. Unlike FIG. 2A, each step in FIG. 2B is not centered around line 200. For each output value, the difference between the actual position of the step and the idealized position as shown in FIG. 2A represents non-linearity in the conversion process. To make a more accurate analog to digital converter it is desirable to remove this nonlinearity. Values stored in calibration memories 130A . . . 130N should adjust for any nonlinearity.
FIGS. 3A–3C illustrate that the nonlinearity error is the result of error components from each of the stages 114A, 114B . . . 114N. FIG. 3A illustrates the linearity error of stage 114A. FIG. 3A is divided into subranges 350, 351 . . . 357. Each of the subranges corresponds to an output value of the stage. The term “subrange” is used because each stage should have a certain value for a range of analog inputs. Accordingly, the ordinate of the graph might be thought of as a range of analog inputs or the specific digital values corresponding to those inputs. The linearity error of stage 114A may be different in each of the subranges.
FIG. 3B shows linearity error associated with stage 114B. Stage 114B has subranges 360, 361, 362, 363. The output of stage 114B may take on multiple values in each subrange defined for stage 114A. For this reason, the subranges for stage 114B are smaller than the subranges for stage 114A. Also, the error pattern for stage 114B repeats in each of the subranges for stage 114A.
FIG. 3C shows this pattern continuing for stage 114C. Stage 114C also introduces linearity errors. The amount of error is different in each of the subranges for stage 114C. Each of the subranges 370, 371, 372 and 373 for stage 114C is smaller than the subranges in stage 114B. The pattern of error repeats in each of the subranges 360, 361, 362 and 363 for stage 114B.
This pattern repeats for all stages, with the subrange per stage getting smaller at each successive stage. An ADC will be most accurate if correction factors can be ascertained and stored in calibration memories for each stage. In practice, it is difficult to determine these values for stages 114B and successive stages. Also, the errors get smaller for successive stages. Thus, despite the fact that FIG. 1 has been generalized to show calibration memories for all stages 114A . . . 114N, such memories have traditionally been used for only the first stage.
Part of the difficulty in ascertaining the correction factors is that the errors from each of the stages are superimposed to create a combined error at the output 120 of the ADC 100. The total nonlinearity error of ADC 100 can be determined, for example, by applying an analog input in the form of a ramp 200. The actual output of ADC 100 will contain non-uniform steps as shown in FIG. 2B. The non-linearity error can be measured by comparing the input voltages at which transitions occur to the values at which such transitions should have occurred with idealized performance as shown in FIG. 2A. However, it is difficult to determine from just the output what error was contributed by each stage.
Also, noise on the analog signal causes the performance of ADC 100 to differ from the idealized form shown in FIG. 2A. Noise is particularly a problem for detecting small errors introduced at stages 114B and smaller stages.
Further, there is not a one-to-one correspondence between the output of each of the stages 114A, 114B . . . 114N and the digital output bits of work 118. Accordingly, when measuring the overall error in analog to digital converter 100 it is often not readily apparent which correction factors need to be loaded into correction memories 130A, 130B . . . 130N.
FIG. 4 represents a plot of non-linearity errors as might be measured for an analog to digital converter. The non-linearity errors shown in FIG. 4 represent the combination of the errors introduced by all of the stages, such as those shown in FIGS. 3A, 3B, and 3C. The plot also reflects noise on the analog signals. FIG. 4 is sometimes called an Integrated Non-Linearity (INL) plot.
Though the errors introduced by all of the stages are blended together in the INL plot of FIG. 4, knowing that the magnitude and repetition rate of errors introduced by each stage follows a pattern as shown generally in FIGS. 3A . . . 3C, might allow identification of the errors produced at each stage. For example, subrange 420 can be identified by a relatively large change in the INL plot such as represented by transitions 412 and 414. The average value of the error in subrange 420 between these transactions might be correlated to one of the subranges 350, 351 . . . 357 shown in FIG. 3A. This approach has been used with some prior art analog to digital converters to identify correction factors for the first stage of a pipelined analog to digital converter. However, for subsequent stages it becomes more and more difficult to identify the component of the overall error contributed by each stage.
One technique that has been used to determine calibration values for higher number stages involved the addition of special hardware to the ADC. This hardware overrides the portion of each stage that outputs the digital bits for that stage. During a test, the input to the ADC is increased until a change in the digital output indicates that a subrange boundary has been crossed. Once the input voltage corresponding to a transition between subranges is determined, the input voltage to the ADC is held constant at that value. The specific stage of the ADC that has changed its output to create the subrange boundary is identified. The digital outputs of that stage are forced to toggle between the value below the subrange boundary and the value above the subrange boundary.
As the output of the stage toggles between subranges, a tester measures the output of the ADC. Measurements taken while the stage is forced to have a value representing the subrange below the boundary represent the error at the upper end of that subrange. Measurements taken while the stage is forced to have a value above the boundary represent error at the lower end of that subrange. By making similar measurements at each subrange boundary, the nonlinearity error in each subrange can be computed and appropriate correction factors to counter this error can be determined.
This approach requires that subrange boundaries be detected by observing the output of the ADC, which can be difficult. It would be desirable to provide a way to calibrate an ADC that does not rely on detecting subrange transitions from the output of the ADC. It would be desirable to accurately determine calibration factors, without requiring additional circuitry in an analog to digital converter to force certain stages into desired output ranges.